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BEQ C_SMALL ; if yes then do a different divide
FDIV ; calculation of low 8-bit result
XGDX
TAB
CLRA
RTS ; result in Acc D
*
C-SMALL LDD BMUL
IDIV ; calculation of high 8 bits (8-bit result)
XGDX
RTS ; result in Acc D
Example 7. HC16 Code to Perform 16-Bit Times 8-Bit
Divided by 16 Bits
calc_tbl_entry
emuls ; multiplier x nominator
edivs ;------------------------ ---> Acc D
; denominator
xgdx place result in accumulator D
rts
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MOTOROLA 45
Application Note
Example 8. HC11 (8-Bit x 8-Bit x 8-Bit) / 9-Bit
********************************************************************
* CALCULATE THE NUMBER OF PULSES FOR A, D, S, R
* Acc A contains the A/D value for calculation
* Acc D contains result
*
* f(x) = (ad_measured + 15) cubed / 400
* or
* f(x) = ( (AD_RESULT) x (AD_RESULT) x (AD_RESULT) ) / 400
********************************************************************
CALC_PULSES ; save A/D value temporarily
STAA TEMP_AD
TAB
MUL ; A/D squared
CLR CALC_SHIFT
READ_5 CMPA #0
BEQ READ_6 ; check if greater than 8-bit value
INC CALC_SHIFT ; if yes then continue
LSRD ; keep track of divisions
BRA READ_5 ; divide by 2
READ_6 LDAA TEMP_AD ; go back and check for 8-bit result
MUL ; restore original A/D result
LDX #400 ; and obtain cubed value
IDIV ; offset for normalized values
XGDX ; divide by offset for best values
READ_7 TST CALC_SHIFT ; place 16-bit result in acc D
BEQ READ_8 ; check if had previously div by 2
DEC CALC_SHIFT ; if not then finish
LSLD ; keep track of multiplies
BRA READ_7 ; go back and check if all mults done
READ_8 RTS ; result in Acc D
Example 9. HC16 (8-Bit x 8-Bit x 8-Bit) / 9-Bit
*******************************************************************
* calculate the number of pulses for a, d, s, r
*
* acc B contains the A/D value for calculation
* acc D contains result
*
* f(x) = (ad_measured + 15) cubed / 400
* or
* f(x) = ( (ad_result) x (ad_result) x (ad_result) ) / 400
**********************************************************************
**
calc_pulses
clra ; ad_result
tde ; placed in accE (making sure upper byte=0)
tba ;
mul ; multiply accA and accB
emul ; Multiply accD and accE (=24 bits E:D)
ldx #400 ;
ediv ; divide E:D by 400 scale factor
xgdx ; place result in accD
rts
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46 MOTOROLA
Application Note
Source Code Compatibility
Comparison A rough estimate of the increased performance of the HC16 over the
of HC11 and HC16 HC11 is that at 16.78-MHz clock the HC16 is nine times faster at 8-bit
Code and operations than a 2-MHz HC11. Taking a theoretical 8-MHz bus speed
Benchmarks HC11 and comparing it with the 16-MHz clock speed HC16 (8-MHz fast
termination bus speed), the performance differential is still
approximately a factor of 2. This is largely due to the improved opcode
efficiency and pipeline of the CPU16 architecture.
For 16-bit and 32-bit calculations, the HC16 is even faster than the
HC11.
Check List " Set the K registers up correctly.
of Changes
" Ensure the CPU registers are stack in interrupt routines.
to HC11 Code
" Remember to add exception routines for the additional vectors.
" Initialize the SIM and peripherals MCR register at the start of the
program.
" Change the register equate addresses if using similar peripheral
functions.
" Check actual timing of software delay loops.
" Make use of the interrupt and arbitration priorities correctly.
" Remember that the HC16 averages nine times the speed of the
2-MHz bus HC11.
" Alter any code that manipulates the CCR. (The bits are moved
about.)
" Check for misaligned stack addressing using PSHA, PSHB, etc.
" Indirect 16-bit offset address operations are now signed values.
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MOTOROLA 47
Application Note
Initialization of HC16 Device
PLL Control A significant change from the HC11 is the control of the clock frequency.
The HC16 SIM module has a phase-locked loop (PLL) and a limp
mode 8-bit oscillator built into the clock circuitry.
In normal operation, the SIM would have a 32-kHz crystal connected to
the EXTAL and XTAL pins. This frequency is then multiplied and phase
locked by the PLL to provide an internal clock frequency of up to 33 MHz
in theory.
In practice, the maximum speed is currently restricted to 16.78 MHz.
20 pF 20 pF
330 k VDDSYN
(NOTE 1)
XFC
0.1 µF
0.1 µF
10 M
XFC PIN VDDSYN 0.01 µF
EXTAL XTAL
CRYSTAL
PHASE COMPARATOR LOW-PASS FILTER VCO
OSCILLATOR
FEEDBACK DIVIDER
CLKOUT
SYSTEM CLOCK CONTROL
SYSTEM
CLOCK
Notes:
1. Must be low-leakage capacitor.
2. EXTAL can be driven with an external oscillator.
Figure 10. Schematic Diagram of the PLL
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48 MOTOROLA
Application Note
Initialization of HC16 Device
After reset, the PLL is preset at 8-MHz clock frequency from a 32-kHz
crystal and so normally will be changed in the initialization section of the
HC16 code.
NOTE: There is a 20-ms lock time for the PLL and altering the W-bit will,
therefore, take this amount of time before the frequency has stabilized.
Changing the X bit has an instantaneous effect since it is outside the PLL
feedback loop. As a consequence, it is necessary to check if a change
to the X bit will take the oscillator over 16.78 MHz before the effect of a
change to the W bit takes effect.
An example is changing the oscillator from 8 MHz to 16.78 MHz where
the W bit = 1 and X bit = 0 (SYNCR(15:8) = $8F). Writing $9F to the
upper byte of SYNCR looks the same as writing $7F to SYNCR(15:8),
but the latter would cause the oscillator to attempt to run at 33 MHz for
a short time as the PLL changes frequency and would certainly cause
the system a fatal error. The correct procedure is to write $3F to
SYNCR(15:8) and then after the SLOCK bit is set to a 1 state (10 to
20 ms later) write $9F to SYNCR(15:8).
A pin called MODCLK controls whether the PLL is enabled. Holding the
MODCLK pin at a logic low during reset will disable to PLL and the
system designer can then use an external high-frequency clock driver
connected to the EXTAL pin.
NOTE: It is not possible to connect a 16-MHz crystal to the EXTAL and XTAL
pins directly.
SRAM Initialization The internal SRAM is disabled at reset. This is because the RAM is fully
Procedure relocatable and the default start address is at the same location as the
reset vectors. The SRAM base address registers should, therefore, be
written and then the module configuration register written to enable the
SRAM.
NOTE: The SRAM base address registers cannot be modified unless bit 15
(STOP control) is set to a 1 (SRAM disabled) and bit 11
(RLCK: RAM base address lock) is cleared. The RLCK bit is a 1-time
writable register after reset.
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MOTOROLA 49
Application Note
When using the HC16Z1 evaluation board, it is often the case that a
memory display window will be pointing to the RAM after it has been
initialized. Typing the reset command will cause the HC16 device to be
reset and the SRAM to be disabled again. The window will now show
garbage data unless it is pointing to a chip-selected address. In addition,
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